--test transformacji fin i init
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity test_fi is
    Port ( din : in  STD_LOGIC_VECTOR (7 downto 0);
		dout : out  STD_LOGIC_VECTOR (7 downto 0));
end test_fi;


architecture Behavioral of test_fi is

component initialtransf is
    Port ( i : in  STD_LOGIC_VECTOR (127 downto 0);
		o : out  STD_LOGIC_VECTOR (127 downto 0));
end component initialtransf;

component finaltransf is
    Port ( i : in  STD_LOGIC_VECTOR (127 downto 0);
		o : out  STD_LOGIC_VECTOR (127 downto 0));
end component finaltransf;

signal tdin, itft, fto : STD_LOGIC_VECTOR (127 downto 0);
begin
tdin(7 downto 0) <=  din(7 downto 0);
tdin(127 downto 8) <= X"AFB3299C0A397BADD4A3C736294B45";

init: initialtransf port map (tdin, itft);
fint: finaltransf port map (itft, fto);

dout(7 downto 0)<=fto(7 downto 0);
end Behavioral;
